1. Field of the Invention
The present invention relates to a method of manufacturing semiconductor devices, and more particularly, to a method of manufacturing semiconductor devices to lower the thickness of the coated photoresist, improve the etch selectivity of the photoresist and the sublayer to be etched, and to effectively form fine patterns having a large aspect ratio.
2. Description of the Related Art
Generally, semiconductor devices are manufactured by carrying out processes including a deposition process, a photolithography process, an etch process, and an ion implantation process, etc.
That is, after forming multiple layers such as a polycrystalline layer, an oxide layer, a nitride layer, and a metal layer, etc. on a semiconductor substrate, patterns of integrated circuits for a semiconductor device are formed on the semiconductor substrate via a photolithography process, an etching process, an ion implantation process, etc.
In the photolithography process, a photoresist is coated on the semiconductor substrate having a certain sublayer formed thereon, the photoresist being a high-molecular photosensitive material, its solubility being changeable due to a chemical reaction by light. A photo mask having fine patterns formed thereon is aligned with the photoresist. Light is irradiated on the photoresist over the semiconductor substrate through the photo mask. So, a chemical reaction occurs on the photoresist, and therefore, the portion of the photoresist exposed to light may turn to more soluble material, or may turn to more nonsoluble material compared with the portion of the photoresist not exposed to light. Then, transformed photoresist is developed by a developer so that a positive or negative type photoresist pattern is formed on the sublayer. The photoresist pattern functions as a mask in the etch process for the sublayer and the ion implantation process after the photolithography process.
Recently, with increasing miniaturization of semiconductor devices and high-integration, the chip size is increased proportional to the increase of the memory capacity, but the size of the cell on which a pattern for a semiconductor device is formed, is decreased. However, to achieve the desired memory capacity with the decrease of the cell size, more pattern should be formed in the limited size of a cell. Therefore, the critical dimension of the pattern is decreased, and the height of the pattern is increased, thus increasing the aspect ratio of the pattern.
At present, because of the limit of the photolithography technique and the limit of the characteristics of photoresist, it is difficult to perform the process satisfying desired process conditions. Therefore, the photolithography process requires that the thickness of the photoresist coated on the semiconductor substrate be as thin as possible, and the etch process requires that the etch selectivity, between the photoresist pattern as an etch mask and the sublayer to be etched, should be as high as possible. That is, the photolithography process can be easily performed if the height of the photoresist is as thin as possible, and the etch process can be easily performed if the photoresist pattern is sufficiently maintained until the etch is completed for the sublayer.
FIGS. 1 to 3 are cross-sections illustrating some problems according to the conventional method of manufacturing semiconductor devices.
FIG. 1 shows that a photoresist pattern 6 is formed to a thickness of about 9500 .ANG. on a polysilicon layer 4 having a thickness of about 1 .mu.m over a semiconductor substrate 2, and then a bridge 8 is formed on the lower portion of the photoresist pattern 6 by carrying out the photolithography process, which means that the exposure is not sufficiently performed because the height of the photoresist is too great.
The thickness of the polysilicon layer 4 and the thickness of the photoresist are same in FIGS. 2 and 3.
FIG. 2 shows that the photoresist pattern 6 is fallen down because the aspect ratio of the photoresist pattern 6 formed on the semiconductor substrate 2 is large.
FIG. 3 shows that the etch selectivity of the polysilicon layer 4 to be etched, and the photoresist pattern 6, is not proper, and so, the height of the polysilicon pattern 10 becomes lower than desired because the portion of the polysilicon layer 4 is overetched more than desired, since the photoresist pattern 6 cannot endure until the etch for the polysilicon layer 4 is over. That is, the desired height of the polysilicon pattern 10 after the etch process is H1, but the real height of the polysilicon pattern 10 after the etch process is H2. Therefore, the polysilicon pattern 10 is overetched by the difference between H1 and the H2. The thickness of the photoresist coated for the formation of the polysilicon pattern 10 is determined such that the thickness of a photoresist pattern 6 formed on the polysilicon pattern 10 after the etch process is about 1000 .ANG. to 2000 .ANG. in consideration of the etch process. However, the above problems occur because the thickness of the photoresist and the polysilicon layer 4 are not uniform from wafer to wafer used as the semiconductor substrate 2, and from point to point in a wafer, which is more serious the larger the diameter of the wafer is.
Therefore, the bridge and the polysilicon pattern 10, its height being lower than desired, reduces the production yield because they degrade the characteristics of semiconductor devices. Also, the fallen photoresist pattern 6 functions as particles in the following etch process, or the ion-implantation process.